A continuing goal for semiconductor memory devices has been to increase storage capacity while not increasing overall device size. Decreases in device size can be accomplished with improvements in process technology that allowing generational "shrinks" of existing designs. Such approaches, however, typically provide only incremental reductions in device size.
An even more desirable way of decreasing device size is to arrive at some way of reducing the number of circuit devices (e.g., transistors, resistors, capacitors) in a memory cell. Decreasing the number of circuit devices can lead to a much higher degree of memory cell integration, thereby allowing for significant increases in storage capacity without increases in overall device size.
One particular type of memory device where increased cell integration continues to be a valuable goal is the static random access memory (SRAM). A conventional SRAM cell may typically include a pair of driver transistors, a pair of access transistors, and a pair of load devices.
One version of a conventional SRAM cell is the six transistor (6-T) cell. In a 6-T cell transistors are used as load devices. Other versions of such a conventional SRAM cell may include resistors as load devices. While memory cells that include resistors as load devices are often referred to as "4-T" cells, to avoid confusion with the type of memory cell discussed in more depth below, such four transistor, two resistor-type memory cells will also be referred to as 6-T cells. In both types of conventional 6-T cells, load transistors/resistors maintain nodes within the memory cell at complementary potentials. In a read operation, such complementary potentials can be placed on digit lines to generate a differential voltage. When such a differential voltage reaches a predetermined potential, the differential voltage can be amplified by a sense amplifier.
In conventional 6-T type memory cells, greater integration has included increasing the number of memory cells that are connected to digit lines, resulting in longer digit lines. However, such an approach increases the load capacitance of such digit lines. Consequently, the time required for digit lines to develop a sufficient differential voltage for a sense amplifier can be longer. This can limit the read operation speeds for such semiconductor memory devices. One approach to address such a drawback is set forth in Japanese Unexamined Patent Application No. 8-287691. Japanese Unexamined Patent Application No. 8-287691 discloses an SRAM circuit having six-transistor memory cells connected to digit lines that are disposed in a latitudinal direction, but divided in the longitudinal direction, to thereby reduce the load capacitance of the resulting digit line segments.
In an attempt to arrive at greater device integration, a "true" four-transistor SRAM memory cell has been proposed. Such a SRAM memory cell does not include load devices, and will be referred to herein as a four-transistor memory cell. A four-transistor memory cell an provide significant increases in integration by reducing the number of circuit devices per cell by one third over 6-T cell approaches. One example of a four-transistor type memory is shown in Japanese Unexamined Patent Application No. 5-62474.
Referring now to FIG. 3 a four-transistor memory cell is shown in a schematic diagram. A four-transistor memory cell may include two driver transistors NMOS1 and NMOS2 arranged in a flip-flop configuration. That is, the drain of driver transistor NMOS1 can be connected to gate of driver transistor NMOS2, while the drain of driver transistor NMOS2 can be connected to the gate of driver transistor NMOS1. The sources of driver transistors NMOS1 and NMOS2 can be connected to a common potential, ground (GND) for example. A four-transistor memory cell may further include two access transistors PMOS1 and PMOS2. Access transistor PMOS1 can have a source connected to a digit line D and a drain connected to the drain of driver transistor NMOS1 at a node N1. Access transistor PMOS2 can have a source connected to a digit line /D and a drain connected to the drain of driver transistor NMOS2 at a node N2. Access transistors (PMOS1 and PMOS2) can have gates that are commonly connected to the same word line WL.
In a read operation for the above-described four-transistor memory cell, a word line WL can be set to a low potential to select a memory cell. With a word line WL low, access transistors PMOS1 and PMOS2 can be turned on connecting nodes N1 and N2 to digit lines D and /D, respectively. A difference in potential at nodes N1 and N2 can be placed on digit lines D and /D and amplified by a sense amplifier (not shown). In this way, data can be read from a four-transistor memory cell.
In a write operation for the four-transistor memory cell of FIG. 3, a word line WL can be set to a low potential to select a memory cell. With a word line WL low, access transistors PMOS1 and PMOS2 can connect nodes N1 and N2 to digit lines D and /D, respectively. In this state, a node (N1 or N2) in a SRAM cell can be driven high by way of a digit line D or /D. In the event the node was previously at a low potential, the node can be charged through a corresponding access transistor (PMOS1 or PMOS2), thereby "toggling" the SRAM memory cell to store the desired logic value.
In the four-transistor memory cell of FIG. 3, data may be retained by supplying power to a digit line (D or /D) with a precharge transistor (not shown). With power supplied to a digit line, a subthreshold leakage current can pass across the source-drain path of an access transistor (PMOS1 of PMOS2) and thereby maintain a corresponding storage node (N1 or N2) at a high potential. As one particular example, if reference is made again to FIG. 3, if it is assumed that node N1 is at a high potential with respect to node N2, driver transistor NMOS2 can provide a relatively low resistance path between the ground potential and node N2. Node N1 can be maintained at a high potential by a subthreshold leakage current (Ioff) flowing through access transistor PMOS1. This is in contrast to a six-transistor memory cell arrangement where node potentials are maintained by load transistors/resistors within each memory cell.
While four-transistor memory cells provide for the possibility of SRAM devices of greater density, it not believed that conventional approaches to such devices have yielded practical results.
Experimentation on four-transistor memory cell SRAM devices have been performed. In particular, read and write operations for such a device have been examined. It has been found that conventional approaches to four-transistor SRAM devices do not appear to generate a sufficient potential difference between digit lines to obtain read operations that are reliable and/or fast enough.
Experimentation has also be been performed on four-transistor memory cell SRAM devices that include segmented digit lines as shown in Japanese Unexamined Patent Application No. 8-287691 described above. Such experimentation has revealed that such an conventional approach may still suffer from the drawbacks noted above. Namely, a sufficient potential difference between digit lines may not be generated, preventing reliable read operations and/or a read operations that are slower than desired.
It would be desirable to arrive at some way of implementing a four-transistor SRAM circuit that can provide more reliable and faster read operations than conventional approaches.